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WL800
2.5GHz Frequency Synthesiser Preliminary Information
DS4583 ISSUE 1.6 October 1997
The WL800 is a low power single chip frequency synthesiser. The circuit is fabricated on Zarlink Semiconductor HG process and operates from a supply voltage of 2.7 - 3.6V. It is designed to work with the Zarlink Semiconductor WL600C RF and IF circuit and the WL102 WLAN controller chip which together make up the DE6038 frequency hopping Wireless Local Area Network (WLAN) transceiver.
Ordering Information
WL800/KG/TP1R
Features * * * * * * * Low power consumption 2.5GHz input 144 frequencies, 1MHz steps (20MHz crystal) Forms complete phase locked loop using external VCO and loop components Serially programmed via 3 wire bus Contains anti-modulation circuit Part of DE6038 Chip-set (WL600C, WL102)
Figure 1 - Pin connections - top view
PIN 1 IDENT
TQFP 32
Related Documents
WL600C, WL102 datasheets
Absolute Maximum Ratings
Supply Voltage Vcc 4VDC Transmit/Receive and -0.5VDC to Vcc +0.5VDC Standby Input Prescaler Inputs Pins 30 &31 No DC. Externally Capacitively Coupled. Output Current (any output) TBD mA Junction temperature Tj 150C ESD protection: 2kV Operating temperature -20 to +85C
WL800
Preliminary Information
Device PIN OUT
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 REFERENCE VCC1 CS-DATA CS-CLK CS-LOADB STDBYB VEE1 ISET ICP VEE3 TXD COM CAP RCOMP IDOUT TXRXB VARICAP VCC3 LOOPFILTER CPUMPREF CPUMPOUT VEE2 SYSCLK XTAL XTALB VCC2 FREF LKCAP LCKDETB FV VEE5 VCC VCOIPB VCOIP TYPE VCC IN IN IN IN GND DESCRIPTION Power for serial data bus Channel Data in (Synth Programming) Data Clock (Synth Programming) Data Enable (Synth Programming) Power down control Active = Logic 1 Standby = logic 0 Ground connection Set modulation current Set charge pump current Ground connection Modulation data in Compensation capacitor for modulation data Resistor for V/I converter Modulation data out Transmit/Receive control Transmit = Logic 1 Receive = Logic 0 Control V to varicap in VCO Power for charge pump and loop amplifier and modulator Loop filter out (Loop Filter Components) Charge pump reference voltage Charge pump out (Loop Filter Components) Ground connection Reference (system) clock out Crystal connection (Differential) Crystal connection (Differential) Power for reference oscillator Reference frequency monitor Lock detect capacitor Lock detect output VCO frequency / (NM+A) monitor Ground connection Power for prescaler, AM counter Ref divider, phase detector and lock detector Prescaler INPrescaler IN+
GND IN OUT OUT IN OUT VCC OUT OUT GND OUT
VCC OUT OUT OUT GND VCC IN IN
2
Preliminary Information
21 12 23 22 REF SYSCLK RCOMP XTALBB XTAL2 XTAL1 OUT VCAP CHARGE CAP BUFFER
WL800
1,16,24,30 Vcc
28 FV
6,9,20,29 14 Vee TXRXB
COMP COMPCAP 11 IDOUT 13
STANDBY STDBYB 5 DATA BUFFER
DIN TXD 10
MOD COMP
REF OUT BUFFER
REFERENCE OSC
DIVIDE BY 20 FREF 25
ISET 7
LKCAP 26
VCOIP 32 VCOIPB 31
PRE AMP
PRE-SCALER
A COUNTER
M COUNTER
PHASE DET & CHARGE PUMP
LOCK DETECT
LKDETB LCKDETB 27
INPUT REGISTER
1/3
LOOP FILTER 17
DATA CS-DATA 2
CLK CS-CLK 3
ENABLEB CS-LOADB 4
ICP 8
CPUMP REF 18
CPUMP OUT 19
VARICAP 15
Figure 1 - WL800 block diagram
3
WL800
Preliminary Information
Electrical Characteristics
These characteristics are guaranteed over the following conditions (unless otherwise stated): TAMB = -20C, to +85C, Vcc = 2.7V to 3.6V Characteristic MIN Supply current (total) Transmit Receive Supply current in standby PROGRAMMING INPUTS Logic low voltage Logic high voltage Input current Data clock frequency (1/tclock) Data/Enable set up time (t set up) Enable hold time (t enable) Positive clock pulse width (tp) Negative clock pulse width (t neg) STANDBY INPUT Logic low input voltage Logic high input voltage Input current Standby to operate time Value TYP 37 35 3 MAX 50 50 5 mA mA mA Unit Condition
0 0.8Vcc
0.4 Vcc 1 20
10 10 20 20
V V A MHz ns ns ns ns
Input level high See Fig. 2 See Fig. 2 See Fig. 2 See Fig. 2 See Fig. 2
0 Vcc -0.7 100 3
0.8 Vcc 150 -150
V V A A s
Circuit powered down Circuit powered up Circuit powered up Circuit powered down *References operational (see note 1)
TX/RX INPUT Logic low input voltage Logic high input voltage Input current REFERENCE OUTPUT Reference output frequency Reference clock output voltage Reference output impedance Mark Space ratio Rise time Fall time Crystal Drive Levels required
0 Vcc -0.7
0.8 Vcc 10
V V A
Receive mode Transmit mode
20 200 -2% 250 600 50/50 300 +2% 15 15
MHz mVp-p Ohms ns ns mV
With 20MHz crystal With 15pF load With 15pF load
200
Pins 22,23 differential
4
Preliminary Information
Electrical Characteristics (continued)
These characteristics are guaranteed over the following conditions (unless otherwise stated): TAMB = -20C, to +85C, Vcc = 2.7V to 3.6V Characteristic MIN LOCK DETECT CIRCUIT Smoothing capacitor charge/ discharge current Threshold voltage Output high voltage Output low voltage PHASE DETECTOR AND CHARGE PUMP Comparison frequency Charge pump output current Up down current matching Reference voltage CHARGE PUMP OP-AMP First Stage: High output voltage Low output voltage Second Stage: Filter drive amplifier output current Filter drive amp output swing Vcc-1.05 80 Value TYP 110 Vcc-0.3 1.8 Vee Vcc 0.5 MAX 150 A V V V Unit Condition
WL800
Determined by application. On smoothing capacitor I out = 10A I out = 0 A
1 1 5 Vcc-0.7
MHz mA % V
Divided crystal reference Rpin 8 = 10k
2.4 0.3 1 0.77
V V mA Vp-p
PRESCALER Input drive voltage Maximum operating frequency Input Impedance
40 3 330 0.5pF
200
mV rms GHz
TRANSMIT DATA INPUT Logic low Logic high TX DATA OUT Logic 0 output current Logic 1 output current Output current in receive mode
-60 +60
-100 +100
A A
Rsource=20k
25
50
100 200
A nA A
Set by external resistor on pin 7 Leakage Current Equal to 0.5 mod current
25
5
WL800
Preliminary Information
Electrical Characteristics (continued)
These characteristics are guaranteed over the following conditions (unless otherwise stated): TAMB = -20C, to +85C, Vcc = 2.7V to 3.6V Characteristic MIN MOD. CURRENT INPUT Mod current set pin current COMPENSATION CAP PIN Compensation current Compensation current matching Compensation capacitor voltage Compensation capacitor voltage CPRef 0.02 88 -120 VCAP CHARGE Settling Time Charging Current Offset Voltage COMPENSATION VtoI (CAPBUFFER+RCOMP) Compensation current into Loop Filter Max. Compensation current CAPACITOR BUFFER Offset Voltage External Resistor RCOMP CPRef 98 -98 -25 2 CPRef +0.02 +110 -88 A % V mV mV Set by external resistor on pin 7. R=47k. Compensation capacitor 8.2nF Receive mode 1 MHz data, 32bits `0' 1 MHz data, 32bits `1' Value TYP 25 MAX A Set by external resistor on pin 7. R = 47k Unit Condition
100 20 15
s mA mV
Receive mode Receive mode. Vcap initially at 0 V. Receive mode.
+52.08 -52.08 1.666
nA nA mA
Per 1us of databit 0 Per 1us of databit 1 for 32 bits(1) at 1MHz
15 58000
mV Ohms
Note: 1. Standby to operate time refers to the time for internal current references to become operational.
6
Preliminary Information
Functional Description
Reference Frequency The reference frequency is generated using a 20MHz crystal in conjunction with an on chip oscillator maintaining circuit. A buffer circuit provides a low level voltage output signal at the crystal frequency to drive the logic in the protocol and control chip. The crystal frequency is divided by 20 to provide the reference signal to the phase comparator. Counters / Dividers An external oscillator is used to feed the input of the preamplifier in the synthesiser, (this isolates the counters from the oscillator and reduces the level of drive signal required by the synthesiser). The output of the preamplifier drives a dual modulus prescaler with ratios of 48/49, which in turn then drives the standard A-M counter arrangement. The A counter then provides the modulus control signal back to the prescaler. The counter system has an overall division ratio given by the formula MN+A where N is the lower divide ratio of the prescaler (48). The divide ratio of the M and A counters is programmable to allow the oscillator to be tuned over the required frequency range of 144 channels at 1MHz spacing. The M count ratio can be programmed over the range 49 to 52 and the A counter from 1 to 48 giving a total divide ratio from 2353 to 2544 which is greater than necessary to tune the required frequency range. Programming The programming data for the synthesiser is entered via a three wire serial data bus consisting of Enable, Clock and Data signals. The enable signal is taken low at the start of the programming sequence and remains low for the duration of the 8 serial data bits. A positive clock edge is required to strobe each data bit into the input register. When all 8 data bits are entered, the enable pin is taken high forcing the counters to zero and preloading the new count data when the counter is next clocked . The charge pump is disabled for a short period after the enable pin goes low to prevent glitch energy being transferred to the VCO. Phase Detectors
WL800
A conventional digital phase frequency detector incorporating dead band suppression is used in conjunction with a charge pump to steer the VCO. An internal op-amp maintains the charge pump pin at the same voltage as the charge pump reference by virtual earth principles. The op-amp is split into two parts with the first section having a relatively low current drive capability but including the high gain stages of the amplifier. The second stage has a controlled voltage gain of 1/3 but high input impedance and low output impedance. This minimises loading to the high output impedance of the first stage and provides sufficient drive current via the loop filter to maintain virtual earth at the charge pump output. The output from the first stage is designed to swing close to the positive and negative rails so as to provide maximum voltage swing to the varactor controlling the VCO. A compensating capacitor can be connected to this point to stabilise the amplifier. A lock detect output (active low) is provided to give an indication to the controller that the phase locked loop is locked, preventing transmission on illegal frequencies. Antimodulation The WL800 contains a data buffer circuit which accepts transmit data from the CMOS controller circuit and converts the CMOS input to a tristate current output for driving the transmit spectrum shaping filter. The buffer gives zero current for a logic "1" input, a high current (+2I) for a logic "0" and a current midway between the two (+I) for use during the transmit amplifier power up/down period and during receive. This function prevents the synthesiser centring its frequency on either a logic "1" or "0" and removes the possibility of overmodulation at the start of a transmission. The amplitude of the output current and therefore modulation index of the radio is controlled by an external resistor connected to ground. A data compensation path is included which counteracts the tendency of the PLL to drift back to centre frequency when the data is non-white. This is achieved by charging an external capacitor with a current +I when data is low, and discharging it by a current -I when data is high. The capacitor voltage, which then represents an integrated form of the data is converted to a current via a buffer and an external resistor (RCOMP), and fed into the Loop Filter in addition to the Phase Detector output. During Receive Mode, the capacitor is charged to the Charge Pump Reference voltage.
7
WL800
Preliminary Information
WL800 Programming
Frequency MHz 2357 2358 2400 2401 2448 2449 2496 2497 2498 2499 2500 Notes:
A counter Value 5 6 48 1 48 1 48 1 2 3 4
M counter Value 49 49 49 50 50 51 51 52 52 52 52
6 bit binary A Value d0-d5 101000 011000 000011 100000 000011 100000 000011 100000 010000 110000 001000
bit binary M Value d6-d7 00 00 00 10 10 01 01 11 11 11 11
1.The binary data is in reverse order. 2.The data is programmed with bit d7 first and d0 last d0 d1 d2 d3 A counter d4 d5 d6 d7 M counter
Timing Diagram
DATA CS_DATA
t set up
t neg
t clock
CLOCK CS_CLK
CS_LOADB
tp
DATA ENABLE
t enable
Figure 2 - Timing diagram
8
Preliminary Information
Control Signals Control Line STDBYB TXRXB LCKDETB Logic `0' Standby Receive Locked Logic `1'
WL800
Active Transmit Unlocked
9
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Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved.
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